Secrets Sauce of Creating a Digital Corner
KeywordsOCV (On Chip Variation), AOCV (Advanced OCV), POCV (Parametric OCV), SOCV (Statistical OCV), LVF (Liberty Variation Format), CCS (Composite Current Source), NLDM (Non-Linear Delay Model), STA (Static Timing Analysis), VLSI characterization, timing variation model
In this article, we'll review what factors contribute to global variation and how do they lead to defining digital corners.
Process variation is result of unpredictability of process parameters (like oxide thickness, channel length, channel width etc) during IC fabrication process. This variation affects electrical characteristic (current and voltage response) of an IP (circuit, cell or design) built with these devices in a significant manner. Analog/AMS flows do not create corners, since they perform through analysis of their designs like AC analysis, sensitivity analysis, pole-zero analysis depending on the circuit type. Digital flows, on the other hand, perform timing, power and noise analysis as verification before sign-off using limited set of conditions called digital corner.
Global Variation in Process Parameters
Global process corners are obtained by performing Monte-Carlo analysis on device parameters (like dopant concentrations etc.) that are known to vary equally for all transistors from wafer to wafer. Monte-Carlo analysis is a well-known statistical method to determine the relationship between factors affecting variation. Generally, Monte-Carlo method (or a similar one) is applied on parameters measured and recorded on devices simulated/manufactured. Statistical spread (aka sigma) is measured and boundaries (typically 3-sigma away) are marked as local corners.
Historically, speed (or timing) of NMOS and PMOS transistors is used to determine process corner for digital implementation and analysis flows. A process corner is named with two letters – first letter is assigned to the speed of NMOS device and second letter is assigned to the speed of PMOS device. Typically, letters used to denote speed are S for slow, F for fast and T for typical. Predetermined values of process parameters for NMOS device is combined with those of PMOS device giving us 9 corners (SS, ST SF, TS, TT, TF, FS, FT and FF). Five of these corners are of interest for digital implementation and analysis, since they represent the extreme limits within which devices are guaranteed to be functional with different properties.
Traditionally three global corners (FF, TT and SS) have been used for timing sign-off and major foundries provide cell libraries in these three corners combined with varying environmental conditions (such as voltage and temperature). However other effects like temperature inversion at advanced nodes below 40nm make it necessary to consider more than three corners for sign-off.
Local Variation in a Process Corner
Local variation is random by nature and appears everywhere on die. These variations are uncorrelated and manifest themselves around global corners as well. In the picture showing global corners, blob represents local process variation. Combination of extreme device parameter values for global corner and local corners is called total corner.
For digital implementation flows, global corners are predetermined and fixed. Determination of local corner is left as an analysis/modeling exercise. Statistical BSIM models are provided for device parameters exhibiting local variation. Timing characterization is performed with these statistical models to generate (timing) variation model.
Voltage variation on the chip is mainly caused by IR drop of resistive Power-Ground supply lines. During the normal course of chip operation, integrated circuits cause variety of activity and transitions in the cells. This activity causes cells/macros/circuits to draw current from PG supply lines, which in turn causes voltage to vary across PG supply line. This drop is main source of voltage variation on the chip. This falls under systematic variations affecting performance of circuits and is used as part of on-chip variation models during static timing analysis.
Power dissipation is main cause of temperature variation on chip. Because activity and transitions in the chip, resistive power (i2R) causes temperature to rise unevenly throughout the chip. High activity regions cause more power dissipation and elevate the temperatures locally. These local regions are called hot-spots of the chip and may raise overall temperature of the chip. Increase in temperature affects chip-performance adversely because of reduced carrier mobility and increase in interconnect resistance. Temperature variation is used as part of on-chip variation models during static timing analysis.
Putting it altogether
Process, Voltage and Temperature are three corner stones of a digital corner. Each one of them are combined to find worst-case and best-case performance of VLSI IPs (cells, circuits and designs). Extreme and typical condition are combined to create a corner. This is reflected in the group operating_conditions inside a liberty file. So whenever you see a block in the header of a liberty file like below, just know that this simple looking mostly useless set of statements hide ton of work behind the scenes.
process : 1;
voltage : 1.8;
temperature : 25;
tree_type : balanced_tree
In this article, we learnt that how a digital corner is created for a library starting from studying global process parameters and binning the conditions to reflect process comers like SS, TT, and FF. Later we reviewed, how voltage and temperature condition are added to process corners to create a digital corner for sign-off.
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