Connecting Dots between PVT Variation and Timing
KeywordsOCV (On Chip Variation), AOCV (Advanced OCV), POCV (Parametric OCV), SOCV (Statistical OCV), LVF (Liberty Variation Format), CCS (Composite Current Source), NLDM (Non-Linear Delay Model), STA (Static Timing Analysis), VLSI characterization, timing variation model
In this article we start need for PVT variation modeling by highlighting effect of PVT variation on timing, power and noise models.
Process variation is result of unpredictability of process parameters (like oxide thickness, channel length, channel width etc) during IC fabrication process. This variation affects timing of the circuits built with these devices in a significant manner. It is therefore, necessary to understand, measure, model and analyze effect of process variation for digital implementation, analysis and sign-offf timing models.
Local variation is random by nature and appears everywhere on die. These variations are uncorrelated and manifest themselves around global corners as well. In the picture showing global corners, blob represents local process variation. Combination of extreme device parameter values for global corner and local corners is called total corner.
For digital implementation flows, global corners are predetermined and fixed. Determination of local corner is left as an analysis/modeling exercise. Statistical BSIM models are provided for device parameters exhibiting local variation. Timing characterization is performed with these statistical models to generate (timing) variation model.
Voltage variation on the chip is mainly caused by IR drop of resistive Power-Ground supply lines. During the normal course of chip operation, integrated circuits cause variety of activity and transitions in the cells. This activity causes cells/macros/circuits to draw current from PG supply lines, which in turn causes voltage to vary across PG supply line. This drop is main source of voltage variation on the chip. This falls under systematic variations affecting performance of circuits and is used as part of on-chip variation models during static timing analysis.
Power dissipation is main cause of temperature variation on chip. Because activity and transitions in the chip, resistive power (i2R) causes temperature to rise unevenly throughout the chip. High activity regions cause more power dissipation and elevate the temperatures locally. These local regions are called hot-spots of the chip and may raise overall temperature of the chip. Increase in temperature affects chip-performance adversely because of reduced carrier mobility and increase in interconnect resistance. Temperature variation is used as part of on-chip variation models during static timing analysis.
Effect of PVT variation
Variation in process parameters, voltage and temperature affects electrical response (namely voltage and current response) of overall IP (cell, circuit or design). Since timing, power and noise characteristics are derived from electrical response of the IP, PVT variation affects timing, power and noise characteristics as a second order effect. However PVT variation does not affect timing, power and noise equally. It tends to affect timing analysis way more than power and noise. An example of that is shown in the next figure, which shows PVT variability effect as delay uncertainty as large part of clock cycle.
This timing uncertainty (aka guard banding or over-design) must be accounted as variation timing margins during design and analysis. As process nodes reduce, this variation increases and consumes large part of clock cycles in timing paths. Therefore, it demands realistic and granular modeling.
In this article, we reviewed cause and effect of Process, Voltage and Temperature (PVT) variation and how it leads to margin and over-design.
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