Miller Capacitance Characterization

Post date: Aug 26, 2014 1:21:03 AM

Keywords: cell characterization, input capacitance characterization

What is miller capacitance?

Simply put- miller capacitance is nothing but coupling capacitance between input and output of a circuit. This effect was first identified by John Milton Miller - a noted electrical engineer of twentieth century.

Increase in input capacitance of an electrical circuit, caused by presence of miller capacitance is called Miller effect. This phenomenon is more generally described in Miller Theorem.

Why is Miller capacitance important?

Miller capacitance changes node/pin capacitance of a circuit. This changed capacitance, if not captured accurately during circuit characterization impacts accuracy of all analyses including static timing analysis, power analysis and noise analysis among others.

Characterization of miller capacitance

This is a general proof, and is applicable to circuits of all logic families including TTL, ECL and CMOS and others. Later we'll limit our attention to cmos circuits and attempt to simplify characterization method.

Sign up for blog updates

Generic buffer/amplifier setup for miller capacitance characterization

In the picture, miller capacitance is shown as CM connected across a buffer/amplifier. Also connected is input capacitance Ci at input and voltage source Vo at output. Assuming current flowing in the buffer is negligible, Kirchoff Current Law dictates that current flowing in two capacitors is equal:

Miller Capacitance Equation 1

If we change value of input capacitance as C1 and C2 at input, apply two voltage sources Vo1 and Vo2 at the output, we can measure changed voltage across Ci1 and Ci2 as Vi1 and Vi2 respectively. Putting these values in equation above, we get

Miller Capacitance Equation 2

This equation is useful for determining driver strengthening (weakening) by aggressor during noise analysis. To find increase in input capacitance, one can exchange Ci and Vi nodes and apply same equation to find miller capacitance. Input miller capacitance is a useful metric for static timing and power analysis. Characterizing input miller capacitance in isolation, however, is not very useful in static analyses. Since static methods will be needed to compute increased loading effect of miller capacitance.

One such method will be to use miller coefficient. This is only a coarse approximation. More accurate, computationally efficient and industry prevalent method is to account for miller capacitance during input/receiver capacitance characterization. Modern current source models (CCS and ECSM) granularize input/receiver capacitance to capture dynamic effect of miller capacitance.

Deriving miller capacitance

If we limit our attention to CMOS inverter, we can derive miller capacitance simply by adding gate-to-drain and gate-to-source capacitance of PMOS and NMOS transistors respectively. These capacitance are shown in the picture below.

CMOS intverter miller capacitance

This simplification, however, is not accurate in practice because it ignores other parasitic resistors and capacitors contributed by poly, diffusion, metal, via and other circuit components.


We discussed definition and importance of miller capacitance. We also presented two different method to determine miller capacitance. We compared their accuracy and applicability to different logic families.

© Paripath Inc, 2014. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url and specific direction to the original content.