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Translating CCS timing model into ECSM timing model and vice-versa

posted Aug 12, 2014, 2:56 PM by Rohit Sharma   [ updated Sep 2, 2014, 12:53 PM ]

keywords: CCS (Composite Current Source), ECSM (Effective Current Source Model), STA (Static Timing Analysis)

Delay calculator of static timing analysis engine looks up CCS or ECSM timing models in liberty file, interpolate or extrapolates neighboring points before it uses them in static timing analysis. CCS driver model captures output current flowing through load capacitor. Thus CCS model forces characterization engine to have a non-zero capacitance connected to cell's output. ECSM driver model captures voltage waveform at cell's output. ECSM driver model can capture load sensitivity starting from zero load capacitance, whereas CCS must start from non-zero load capacitor.
cmos inverter voltage current profile
Inverter's current/voltage profile

In the next section, we'll relate these two driver model using basic circuit theory, which defines charge as:
charge across capacitor (q=cv)
where 
q=charge stored in capacitor, 
C=capacitance 
v=voltage across capacitor

Also, Current is a measurement of the flow of electricity and is generally describe as
charge-current equation

Combining these two equations, gives us
current over time through capacitor equation

differentiating and integrating both sides w.r.t time, yields 
current through and voltage across capacitor

These two equations enlighten us that current and voltage is nothing but two faces of charge stored in capacitor. And current can be computed from voltage and vice-versa.

Remember, we said earlier that CCS driver model captures output current flowing through load capacitor and ECSM driver model captures voltage waveform at cell's output. Since we've shown that current can be computed from voltage and vice-versa, it is easy to see that CCS driver model can be derived from ECSM driver and vice-versa.

There are practical accuracy limitations, however. ECSM voltage and CCS current waveform are sampled with far fewer points - typically 10 to 100 times fewer points from reference simulator's output. There is limited accuracy loss, when these points are sampled judiciously from circuit simulator's output. Accuracy loss may become pronounced, in case sampled ECSM voltage waveform is translated into CCS current waveform (and vice-versa) because of missing data.
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