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7 facts every designer should understand about spice simulators

posted Sep 15, 2016, 8:39 AM by Rohit Sharma   [ updated Sep 15, 2016, 9:23 AM ]
Keywords: SPICE (Simulation Program with Integrated Circuit Emphasis), Circuit Simulation, SPICE performance, SPICE capacity, SPICE accuracy, SPICE DC convergence
Category: SPICE simulation

SPICE waveforms

It has been almost five decades since Laurence W Nagel wrote the first circuit simulation engine SPICE (Simulation Program with Integrated Circuit Emphasis) at the University of California at Berkeley in 1970s. It has been morphed into many different commercial versions such as HSPICE. Circuit simulator based on Berkeley spice continue to flood the EDA marketplace. As process node and capacity demands changes, circuit simulators have evolved int three broad categories.
  1. True SPICE (e.g. Synopsys HSPICE)
  2. Fast SPICE (e.g. Cadence spectre APS, Synopsys FineSim)
  3. Hybrid SPICE (e.g. Mentor AFS, Synopsys xa)
Parallel technology is like a herb on SPICE. It is applicable to speed up all three types of simulators, hence not listed as separate categories. The table below summarizes core architecture trade-offs of these simulators.

  True SPICE Hybrid SPICE Fast SPICE
Accuracy golden under 5% upto 15%
Capacity low moderate high 
Performance low moderate  fast 
DC convergence accurate  mostly accurate runs into issues
Circuit Matrix single partitioned partitioned
RC reduction none moderate aggressive
Hierarchical Sim none opportunistic aggressive
Event Wheel no no yes

Next time you run spice, keep this table in mind to determine trade off performance, capacity, and accuracy early in the flow. Let this table be your guide to avoid issues (like DC convergence) in your simulation. Another lazy and effective way to use trade-offs and avoid issues is to use circuit simulation accelerator like PASER .

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