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7 facts every designer should understand about spice simulators

posted Sep 15, 2016, 8:39 AM by Rohit Sharma   [ updated Sep 15, 2016, 9:23 AM ]

Keywords: SPICE (Simulation Program with Integrated Circuit Emphasis), Circuit Simulation, SPICE performance, SPICE capacity, SPICE accuracy, SPICE DC convergence
Category: SPICE simulation


SPICE waveforms



It has been almost five decades since Laurence W Nagel wrote the first circuit simulation engine SPICE (Simulation Program with Integrated Circuit Emphasis) at the University of California at Berkeley in 1970s. It has been morphed into many different commercial versions such as HSPICE. Circuit simulator based on Berkeley spice continue to flood the EDA marketplace. As process node and capacity demands changes, circuit simulators have evolved int three broad categories.
  1. True SPICE (e.g. Synopsys HSPICE)
  2. Fast SPICE (e.g. Cadence spectre APS, Synopsys FineSim)
  3. Hybrid SPICE (e.g. Mentor AFS, Synopsys xa)
Parallel technology is like a herb on SPICE. It is applicable to speed up all three types of simulators, hence not listed as separate categories. The table below summarizes core architecture trade-offs of these simulators.

  True SPICE Hybrid SPICE Fast SPICE
Accuracy golden under 5% upto 15%
Capacity low moderate high 
Performance low moderate  fast 
DC convergence accurate  mostly accurate runs into issues
Circuit Matrix single partitioned partitioned
RC reduction none moderate aggressive
Hierarchical Sim none opportunistic aggressive
Event Wheel no no yes

Next time you run spice, keep this table in mind to determine trade off performance, capacity, and accuracy early in the flow. Let this table be your guide to avoid issues (like DC convergence) in your simulation. Another lazy and effective way to use trade-offs and avoid issues is to use circuit simulation accelerator like PASER .

© Paripath Inc, 2016. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.

Is charge sharing silently killing your design?

posted Jan 29, 2015, 4:24 PM by Rohit Sharma   [ updated Feb 5, 2015, 9:21 AM ]

Keywords: Charge sharing, Charge distribution, Charge redistribution, Operating frequency, Dynamic logic, Domino logic, Failure analysis, Circuit reliability, Circuit analysis, Circuit noise.
Category: Static Design Analysis

Introduction:
Sharing is caring, unless it is as vital as required charge to function your design. As we move down from 20nm and below on designs with low voltages, charge sharing is quickly becoming mission critical problem in high performance custom circuit designs using dynamic logic. Moderate charge sharing may slow down your circuits, while excessive charge sharing may cause functional failure.
In this article, we introduce charge sharing problem, discuss ill effects thereof, and suggest alternates to reduce the effects.

Little About Dynamic Logic
Dynamic logic is up to twice as fast compared to static CMOS and therefore presents itself as a preferred option for high performance custom circuits. An example of dynamic NAND gate is shown in Figure 1. These gates operate with clock  (CLK) signal's precharge and evaluate cycles. Precharge cycle pulls output to logic one and evaluate cycle evaluates input states. 

What is Charge Sharing?
Given capacitors (C2 and C3 in figure 1) on internal nodes are discharged in previous evaluate cycle, output charge (C1 in figure 1) brought by logic-1 during precharge cycle will be shared with internal node C2 in the following evaluate cycle when input B set to zero.
Example of Dynamic Logic Charge Sharing
Figure 1: Charge Sharing Example in Dynamic NAND gate.

This charge sharing may cause output voltage drop and further cause unintentional switch of receivers resulting in functional failure of the chip. Example of 10% voltage drop in NAND gate with 14nm Predictive Technology Model from ASU with high performance models ptm14hp is shown in Figure 2.

Charge Sharing Signal Voltage Drop of a NAND gate at 14nm
Figure 2: Charge Sharing induced Voltage Drop in 14nm NAND gate.

How to Avoid Charge Sharing
Paripath product inCharge analyzes design for charge sharing violations. Paripath inCharge will identify and report violating nodes using ultra-fast and accurate static analysis technology. Once these nodes are identified, employ one of the following techniques to remove violation
  1. Add a secondary precharge PMOS to every other NMOS in evaluation stack. However, it increases chip area and adds to complexity.
  2. Artificially increase load on output. However, it slows down circuits and may add crosstalk.
  3. Increase parallelism of evaluation stack. But It adds area and complexity of the chip.
Conclusion
In this article, we introduced dynamic logic and charge sharing problem associated with them. Later sections were used to explain and demonstrate 10% voltage drop in a 2 input NAND gate at 14nm.

© Paripath Inc, 2015. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.


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