Characterization Blog
Characterizing MSP cells
Keywords: level shifter, differential amplifier, ground level Category: VLSI characterization Introduction: Challenges of characterizing digital cells start to look easy in the face of mixed signal cells with parameters that defy assumptions of digital cells. One of the assumption digital cells make is ground voltage is zero, which does not hold good for mixed signal cells like level shifter, differential amplifiers etc. How does delay measurement change with violation of this assumption is the topic of this article. Below is an example waveform of such a cell. Figure: multi rail wave forms of a differential amplifier Note that this cell appears to have differential inputpair and differential output pair. Input pair switch in different direction from zero volt to 0.73 volt, whereas output pair switched from 0.30 volt to 0.68 volt. Measuring Arc Delay: With changed voltages, one has to come up with new threshold voltages to find delay points. As we discussed in previous blog, delay measurement involves following 8 threshold voltages.
With these definition, we find rail swing for both input and output pins as follows:
Once swing has been determined, one can find input and output voltage levels crossing thresholds as follows:
Conclusion: In this article, we presented method and equations to compute delays with ground voltages other than zero. One can easily extend this method to find equation to compute output slope with ground voltages other than zero. 
Negative delays aren't so negative after all !
Keywords:
Negative propagation delay, Standard cell delay, delay thresholds.
Category:
VLSI characterization
Introduction
You read the term "negative delay" and your engineer mind goes racing creating science fictions  time machine, time generator, noncausal machine and so on. Here are the answers  no, you can't turn circuits with negative delays into a timemachine, you can't go back in time, you can't even increase frequency of a chip. So calm your nerves and allow us to debunk myths behind negative delays. In this article we'll define delays, explain negative delays and sources thereof.
What is propagation delay?
Signal propagation delay is, nothing, but measurement of time between two signal. These two signals could
be anywhere in the circuit, i.e. input and output pins of a cell, two nodes of an RC tree or start
and end point of a time path.
In the context of a cell or circuit, change in input pins state could cause a change in output pin.
Signal is said to have reached a point of no return in the transition, once it crosses a certain
threshold. These thresholds are predetermined for the circuit. They could be different for
rise and fall transition, input and output pin of a circuit or standard cell. These are typically set
at 50 percent of the rail voltage (difference between power and ground voltages) of a signal. In this context
rise or fall (propagation) delay of a circuit/cell is defined as
propagation delay = 50% threshold of output transition  50% threshold of input transition
Under normal circumstances, propagation delay of a circuit/cell is positive, i.e. input signal reaches
its 50% threshold before output signal reaches its 50% threshold.
But, how can delay go negative?
Sometimes cell (typically with strong drive strength) may exhibit negative propagation delay. This does not mean that standard cell's input and output have noncausal relationship. This is simply a manifestation of choice of delay threshold points. Picture below shows an example of negative delay of a simple inverter, when falling input A
transition causes a rising transition at output Y.
Figure: Negative Propagation Delay
It is easy to see in the picture that input signal A starts to fall at 0ps, whereas output signal does not move
from low voltage (ground, VSS or 0.0V) until 235ps. This reinforces our earlier statement about causality of these
two transition. Given rail voltage of 1.2 volt, delay threshold point of 50% translates in to a 0.6V of theshold. Notice that input reaches 0.6 Volt (50 percent threshold of input rail voltage) at 500ps,
whereas output is able to reach this threshold 0.6 Volt (50 percent threshold of output rail voltage) at 467ps.
Using propation delay equation defined above,
propagation delay = 467ps  500ps = 33ps
And there, we witness negative delay for this transition.
So, what causes negative delays?
There could be many reasons for negative propagation delay of a circuit/cell, some of them are given below.
Conclusion
In this article, we defined propagation delay. We, also, saw how a propagation delay could be negative and why does
it not represent noncausal relationship between input and output. In the end, we outlined few probable causes of
negative delays.
Credit
This blog was posted in response to following user question: Q: What is negative propagation delay? by Lingraj Hiremath, Senior Design Engineer. Tata Elxi Limited. 
Demystifying Slew Derate
Keywords:
slew derate from library, slew rate (aka transition time, slope), Liberty^{TM} Format, STA (Static Timing Analysis)
Category:
VLSI characterization
Introduction
Typically liberty library for process nodes below 40nm has a keyword called slew_derate_from_library.
This keyword changes the way designers/EDAtools read signal transition times (aka slew rate or slope)
from library for both input and output pins of the cell. This keyword has bearing on other slew measurement
thresholds, which makes whole picture a bit complex to comprehend. In this article, we'll try to explain slew dertate
from characterization and timing analysis point of view.
Thresholds
Slew is measured between two thresholds  lower and upper. These threshold could be different for rising and
falling transitions. Hence there are total of 4 different thresholds with following keywords
These four thresholds are shown in the picture below
Need for slew derate
Signal slew rates for process nodes 180nm or above were linear between 10 and 90 percent of their rail voltages.
This linearity drove the choice of slew thresholds between 10 percent and 90 percent. This linearity was reduced to a
band of 20 percent and 80 percent for nodes between 180nm and 65nm. It was further reduced to 30 percent and 70 percent.
Latest transition band 3070 percent is only 40 (7030) percent of rail voltage, hence misrepresents slew rate between
rail voltage. Need to translate this new band to a reasonable (more than 50 percent) percentage of rail voltage gave
birth to slew derate.
Example
If we need to represent transition band of 3070 percent to 1090 percent, we'll be multiplying slew rates
(aka transition times) measured between 3070 percent by a factor of 2 to represent it as 1090 percent. Slew
rate is derived from these two bands. This is shown as a simple division below
slew_derate_from_library = (7030)/(1090) = 0.5;
Slew derate for characterization
Input and output slew rates in liberty are stored after applying (i.e. dividing) slew_derate_from_library
factor. Characterization software like guna applies signals with specified slew rate at inputs and measures slew
at output. While reading slew rates from liberty, factor slew_derate_from_library is applied in a reverse fashion
(by multiplying) in order to obtain slew rates between thresholds as specified in the liberty header (see Thresholds
section above).
Input slew rates are multiplied by slew_derate_from_library factor to obtain slew rates between thresholds in the
liberty header. Resulting input slew rate is extended to rail voltage, thereafter. Final input slew rate is
applied in the form on piecewise linear voltage source at input. Assuming, rest of the inputs are tied
to their appropriate signal voltage to cause output transition, characterization software measures output
slew rate between thresholds as specified in the liberty header. This output slew rate is divided before
being stored in new liberty file.
Slew derate for Timing Analysis
Timing analysis also reads slew rates from liberty file. Computing slew rate is further complicated by
the fact that analysis software may read multiple liberty files with different thresholds and
slew_derate_from_library factor. On the top of that, it may have it's own native slew thresholds
(example  20% to 80%). (Note that other types of derating like data/clock path derating is not covered
in this article).
Timing analysis divides designs into timing stages. One Timing stage consists of driver model, net model
and a receiver model. Driver model is derived from delayslew/current/voltage values. Factor slew_derate_from_library
is used is determining library slew between library threshold. Library thresholds are translated
into timing analysis's native threshold using following equation
Once, we have slew value between library threshold, it is easy to translate them into timing analysis' native threshold as follows:
Summary
Slew derating is best understood by keeping in mind the following formula 
slew value_{librarythreshold} = slew_derate_from_library * slew value_{library} ;
VLSI characterization timing model
 VLSI characterization timing model 
Can Your Methodology Survive FinFET Variability?
Keywords:
FinFET structure, 14nm, 16nm, FinFET characterization, CCS Variation, Liberty^{TM} Format, STA (Static Timing Analysis)
Category:
VLSI characterization and variation
What is FinFET?
FinFET device is a three dimensional multi gate MOSFET transistor. Three dimensional FinFET structure contains channel grown over silicon substrate in third dimension with a gate wrapped around it as shown in the figure.
It replaces planar MOSFET transistors with the ones with superior power and performance characteristics. FinFET devices are touted as disruptive technology to maintain the Moore’s Law trend of transistors count of a ICs doubling (approximately) every two years.
Good, Bad and Ugly Side of FinFETs
Good: Superior Power and Performance.
FinFET has superior I_{Dsat} properties compared to planar devices. This means faster transistors for same power or
lower power for same speed compared to planar devices.
Bad: Higher Miller Capacitance
The 3D nature of the fins contributes to higher gate capacitance compared to planar devices. This increased
gate capacitance directly impacts miller capacitance and its effect on stage delay and receiver waveform computation.
In sub20 nm, effect of miller capacitance on delay has jumped to more than 10 percent on a nominal delay
of few hundred picoseconds and therefore can no longer be avoided.
Ugly: Higher Variation
There is a need to contain waveform distortion while sampling output and powerground current and voltage waveforms.
FinFET structure suffers more PVT (Process, Voltage, Temperature) variation than a planer process due to line and finedge roughness.
4 Steps to Avoid Characterization Pitfalls with FinFETs

Comparing NLDM And CCS delay models
VLSI characterization timing model Keywords: CCS (Composite Current Source), NLDM (Non Linear Delay Model), SDM (Simplified Driver Model), STA (Static Timing Analysis)
What is timing model?
A timing model consists of driver model, net model and a receiver model. Driver model and receiver models are typically characterized using a circuit simulator, whereas net model is either estimated (wireload, manhattan or star topology) or extracted from a layout using technology parameters of metal, via and contact etc.
NLDM Driver Model
NLDM driver model characterizes inputtooutput delay and output transition times with sensitivity to input transition time, output load and side input states.
These characteristics are obtained using a circuit simulator with appropriate stimulus to cause output transition. Input stimulus along with input/output measurement/capture points are shown in the picture below.
As seen in the picture, characterization software like guna measure and captures 3 points on sides of active input and active output. These three points are called delay and transition time thresholds. Difference between input delay threshold and output delay threshold is modeled as cell delay and difference between lower and upper transition times on output port is modeled as output transition time. These two parameters  delay and transition times are used to synthesize NLDM driver model shown in the picture below:
NLDM Receiver Model
NLDM receiver model is simply a single capacitor for the entire transition with no sensitivity.
Shortcomings of NLDM model
NLDM only captures 3 output points, which is not sufficient to reflect nonlinearities of circuits at lower geometries (65nm and below) in synthesized driver model during static timing analysis. Classical case of this insufficiency is when driver resistance is order of magnitude less than the impedance of net it is driving (Rd << Znet). Driver model requires more granularity in driver model. CCS timing model eliminate need for this synthesis and hence is able to achieve higher accuracy than NLDM.
Other significant shortcoming of NLDM is in the receiver model. NLDM receiver model fails capture miller effect. This effects dominates delay calculation of STA for very small impedance nets.
CCS Driver Model
CCS driver model is characterized by capturing current waveform flowing into the load capacitor of the cell. CCS driver model also has sensitivity to input transition time, output load and side input states. CCS driver model is essentially a current source with infinite driver resistance, hence it provides better accuracy in cases where net impedance is very very high. Note, CCS timing model does not require synthesis of driver model, captured current waveform is driver model itself.
CCS Receiver Model
CCS receiver model is characterized much like NLDM receiver model with additional granularity to reflect sensitivities like miller capacitance, state of side inputs, input transition times and output load. To accurately reflect effect of miller capacitance on input capacitance and netdelay, it is divided into two parts  C1 and C2. For STA delay calculation, C1 is used in net delay calculation before receiver waveform hits delay threshold point and C2 is used in net delay calculation after receiver waveform hits delay threshold point.
Summary
In this article, we introduced timing model of a VLSI cell. We discussed NLDM (Non Linear Delay Model) of a cell used in STA. In later section, we highlighted shortcomings of NLDM for advanced nodes and CCS (Composite Current Source) as one solution to address them.

Standard Cell Characterization
What is cell characterization?
Cell characterization is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.
Why is cell characterization needed?
No digital chip is possible without cell models. These cell models are produced by cell characterization using commercial softwares like guna. Every digital chip implementation (rtltogdsII) flow requires cell models for analysis (logic simulation, verification, timing, power, noise etc), implementation (synthesis, test insertion, placement, clock tree synthesis, routing) and fixing (engineering change order, rule fixing etc).
How is cell characterization performed?
Cell characterization typically takes cell design extracted as spice circuit and spice technology models. Characterization software like guna from Paripath, analyzes this information to
Figure: cell characterization flow
Cell characterization output
Cell characterization produces following outputs, in no particular order
This article answers main questions on standard cell characterization and model generation. Scope of this topic is VLSI cell/circuits. Please google for solar cell characterization and biocell characterization. Read more on VLSI characterization on Paripath Blog.  Sign up for blog updates 
Miller Capacitance Characterization
Keywords: cell characterization, input capacitance characterization
What is miller capacitance?
Simply put miller capacitance is nothing but coupling capacitance between input and output of a circuit. This effect was first identified by John Milton Miller  a noted electrical engineer of twentieth century.
Increase in input capacitance of an electrical circuit, caused by presence of
miller capacitance is called Miller effect. This phenomenon is more generally described in Miller Theorem.
Why is Miller capacitance important?
Miller capacitance changes node/pin capacitance of a circuit. This changed capacitance, if not captured accurately during circuit characterization impacts accuracy of all analyses including static timing analysis, power analysis and noise analysis among others.
Characterization of miller capacitance
This is a general proof, and is applicable to circuits of all logic families including TTL, ECL and CMOS and others. Later we'll limit our attention to cmos circuits and attempt to simplify characterization method. In the picture, miller capacitance is shown as C_{M} connected across a buffer/amplifier. Also connected is input capacitance C_{i} at input and voltage source V_{o} at output. Assuming current flowing in the buffer is negligible, Kirchoff Current Law dictates
that current flowing in two capacitors is equal:
If we change value of input capacitance as C_{1} and C_{2} at input, apply two
voltage sources V_{o1} and V_{o2} at the output, we can measure changed
voltage across C_{i1} and C_{i2} as V_{i1} and V_{i2}
respectively. Putting these values in equation above, we get
This equation is useful for determining driver strengthening (weakening) by aggressor during
noise analysis. To find increase in input capacitance, one can exchange C_{i} and
V_{i} nodes and apply same equation to find miller capacitance. Input miller capacitance is a useful metric for static timing and power analysis. Characterizing input
miller capacitance in isolation, however, is not very useful in static analyses. Since static methods will be needed to compute increased loading effect of miller capacitance.
One such method will be to use miller coefficient. This is only a coarse approximation.
More accurate, computationally efficient and industry prevalent method is to account for miller
capacitance during input/receiver capacitance characterization. Modern current source models
(CCS and ECSM) granularize input/receiver capacitance to capture dynamic effect of miller capacitance.
Deriving miller capacitance
If we limit our attention to CMOS inverter, we can derive miller capacitance simply by adding gatetodrain and gatetosource capacitance of PMOS and NMOS transistors respectively. These capacitance are shown in the picture below.
This simplification, however, is not accurate in practice because it ignores other
parasitic resistors and capacitors contributed by poly, diffusion, metal, via and other
circuit components.
Summary
We discussed definition and importance of miller capacitance. We also presented two different method to determine miller capacitance. We compared their accuracy and applicability to different logic families.
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Translating CCS timing model into ECSM timing model and viceversa
keywords: CCS (Composite Current Source), ECSM (Effective Current Source Model), STA (Static Timing Analysis)
Delay calculator of static timing analysis engine looks up CCS or ECSM timing models in liberty file, interpolate or
extrapolates neighboring points before it uses them in static timing analysis.
CCS driver model captures output current flowing through load capacitor. Thus CCS model forces characterization engine to
have a nonzero capacitance connected to cell's output. ECSM driver model captures voltage waveform at cell's output.
ECSM driver model can capture load sensitivity starting from zero load capacitance, whereas CCS must start from nonzero
load capacitor.
In the next section, we'll relate these two driver model using basic circuit theory, which defines charge as:
where
Also, Current is a measurement of the flow of electricity and is generally describe as
Combining these two equations, gives us
differentiating and integrating both sides w.r.t time, yields
These two equations enlighten us that current and voltage is nothing but two faces of charge stored in capacitor. And
current can be computed from voltage and viceversa. Remember, we said earlier that CCS driver model captures output current flowing through load capacitor and ECSM driver
model captures voltage waveform at cell's output. Since we've shown that current can be computed from voltage and viceversa,
it is easy to see that CCS driver model can be derived from ECSM driver and viceversa.
There are practical accuracy limitations, however. ECSM voltage and CCS current waveform are sampled with far fewer points 
typically 10 to 100 times fewer points from reference simulator's output. There is limited accuracy loss, when these points are
sampled judiciously from circuit simulator's output. Accuracy loss may become pronounced, in case sampled ECSM voltage waveform
is translated into CCS current waveform (and viceversa) because of missing data.
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CCS Timing Model vs ECSM Timing Model
CCS stands for Composite Current Source and ECSM stands for Effective Current Source Model. Both of these are current source
models and have ability to abstract circuit models for static timing, power, noise and voltagedrop analysis.
Timing model consists of a driver model and a receiver model as shown in next picture.
Delay calculator of static timing analysis engine looks up, interpolate or extrapolates these two models in liberty.
CCS driver model captures output current flowing through load capacitor. Thus CCS model forces characterization engine to
have a nonzero capacitance connected to cell's output. ECSM driver model captures voltage waveform at cell's output.
ECSM driver model can capture load sensitivity starting from zero load capacitance, whereas CCS must start from nonzero
load capacitor. Next picture shows output voltage V(CY) captured in ECSM driver model and output current I(CY) captured in CCS driver model. Next picture shows miller capacitance of inverter contributed by both transistors  nmos and pmos. Receiver model of both models captures miller capacitance of receiver with sensitivity to slope and load.
In the next blog, we'll relate these two driver model using basic circuit theory. Current source receiver models are essentially same with different granularity. Both these CCS and ECSM models capture miller effect as input capacitance with different sensitivity to input transition, input transition times, output load etc.  Sign up for blog updates 
Current Source Models: Historical Perspective
Digital Implementation and analysis flows rely heavily on cell models. These models have evolved through the
years. CCS and ECSM are two dominant models currently in use in the industry today.
CCS stands for Composite Current Source. It is a part of liberty format released and endorsed by Synopsys Inc
and is touted as first in the industry to deliver a complete opensource current based modeling solution for timing,
noise and power.
ECSM stands for Effective Current Source Model. It is liberty extension released in 2001 by Cadence Design Systems and
is claimed as most complete open library format available and holistically models the effects of timing, noise, power,
and variation. It was, indeed, first effort to model long wires with high impedance interconnects.
Accuracy of driver models in delay calculation during static analyses was primary technical reason behind the rise of these
two current source models in early 2000s. ECSM was ahead of curve in modeling long wires with high impedance, when it
was released in 2001. CCS leapfrogged with complete set of modeling in mid2000s. ECSM caught up in the later part of
decade.
These two formats have been released in open source to gain wider industry support. Extensions of ECSM are now released
by the ECSM working group of the OMTAB (Open Modeling Technical Advisory Board) under
SI2 . Whereas ownership of enhancing liberty format including CCS was given to LTAB (Liberty Technical
Advisory Board) under IEEEISTO

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