Comparing AOCV to POCV variation model

posted Oct 25, 2017, 6:29 PM by Rohit Sharma   [ updated Nov 8, 2017, 5:32 PM ]

VLSI characterization timing variation  model
Keywords: OCV (On Chip Variation), AOCV (Advanced OCV), POCV (Parametric OCV), SOCV (Statistical OCV), LVF (Liberty Variation Format), CCS (Composite Current Source), NLDM (Non Linear Delay Model), STA (Static Timing Analysis)

Introduction

In this article we'll discuss performance variation modeling in integrated circuits (IC). 

What is variation?

Statistical variation measures how far a set of  numbers are spread out from their average value. In this article we'll focus our attention to IC performance variation.
Process Variation Distribution Example

Sources of variation affecting performance

Main source of variation affecting IC performance are Process, Voltage and Temperature collectively known as PVT. Combination of PVT set giving extreme performance (minimum delay, maximum delay, typical delay etc) is a global corner. Within this global corner, local variation parameters like etching process, mask alignment and optical proximity correction can vary performance noticeably. These local process variation parameters cause changes in transistor channel length, width, threshold voltage and oxide thickness, which in turn shows up as variation in delay and slew of a cell's timing arc of a single corner library.

What is OCV?

OCV stands for on-chip variation of IC process parameters. OCV is typically used during Static Timing Analysis (STA) to accommodate local variation for process nodes above 90nm. Generally, it is modeled using a simple derate number for data path, clock path, early path and late paths for rise and fall transitions during analysis phase and therefore require no model.

What is AOCV (aka SBOCV)?

AOCV stands for Advanced OCV and SBOCV stands for Stage Based OCV. To clarify the need for AOCV, consider two cases of single and multiple cells. Single cell in isolation exhibits larger delay variation compared to number of cells in a path. This is because some of the random variation effect tend to cancel out in group. For example if one inverter shows 5% variation in performance, 10 inverters connected together will show variation much less than 50%. Using one number (as in OCV for all cells) in STA results in pessimism. AOCV has been shown to reduce pessimism in node 65nm and below and is part of main stream sign-off methodology for nodes 40nm and below.
AOCV table contains derate numbers for cells used for data path, clock path, early path and late paths for rise and fall transitions.
Below is one example for AOCV table:

object_type : lib_cell
rf_type : rise
delay_type : cell
derate_type : late
path_type : data
object_spec : 10nmlib/BUF_X4
depth : 1 2 3 4 5 6 7 8 9 10
table: 1.183 1.145 1.122 1.109 1.0901 1.0801 1.0736 1.0650 1.0601 1.055
Example: AOCV derate table

Table above shows keywords and values for rf_type (rise or fall), derate_type (early or late), path (data or clock) and object_type (lib_cell or net). Last two indices depth and table representing stage depth of the path and applicable derate value for the path.
Picture below shows early derate (red color) and late derate (green color) numbers (on y-axix) as a function of no. of stages (on x-axis). Note that both these number tend to converge to 1.0 as number of stages go up. It manifests random variation cancellation with higher number of stages in the path. 
AOCV table for rise clock buffer path
Figure: early and late AOCV derate for clock path.

What is POCV?

POCV stands for Parametric On-Chip Variation. POCV was proposed to address shortcomings of AOCV/SBOCV for granularity, accuracy, Common path pessimism removal and half cycle paths. POCV eliminates the need for stages, path type and corner delay to find delay derate during characterization phase. It pushes these steps in to static timing analysis, thereby addressing shortcomings of AOCV/SBOCV.  POCV has been shown to reduce pessimism in node 20nm and below and is part of main stream sign-off methodology for nodes 16nm and below.

What is SOCV?

SOCV stands for statistical OCV, a term proposed by cadence design systems. It is simular to POCV

What is LVF?

LVF is a libertyTM extension for variation models proposed by LTAB at IEEE-ISTO. It attempts to unify all types of variation models including AOCV, SBOCV and POCV. It adds granularity to POCV by adding slope and load sensitivity.

ocv_sigma_cell_rise ("pocv_template_4x4") {
    sigma_type : "late";
    index_1("0.01, 0.04, 0.12, 0.80");
    index_2("0.01, 0.02, 0.03, 0.10");
    values( "σ11, σ12, σ13, σ14", \
            "σ21, σ22, σ23, σ24", \
            "σ31, σ32, σ33, σ34", \
            "σ41, σ42, σ43, σ44", );
}
Example: POCV sigma value in LVF format
Example above shows POCV sigma (σij) value in LVF format. Typically index1 is defined as slope axis and index2 is defined as load axis.

Comparing AOCV and POCV

AOCV (aka SBOCV)
POCV
delay derates delay sigma
NA slew sigma
constraint derates constraint sigma
logic stage based NA
derates for cell and transition sigma for each timing arc
NA sensitive to input slew (part of LVF)
NA sensitive to output load (part of LVF)
derate is multiplied for path delay sigma is looked for path delay
NA accurate modeling constraints like MPW and half cycle paths
 NAreduces pessimism for graph based STA and optimization
 NAenables mean and sigma reports for STA

Variation models usage

Graphic below shows usage of variation models by process nodes.
On-Chip Variation Model (OCV, AOCV, POCV) Usage over process nodes

Summary

In this article, we discussed variation and sources thereof. Later we discussed reasons for better modeling of variation giving us AOCV and further improvement in POCV. In the end we compared AOCV to POCV.
© Paripath Inc, 2017. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.


Characterizing MSP cells

posted Oct 2, 2015, 3:42 PM by Rohit Sharma   [ updated Oct 2, 2015, 3:43 PM ]

Keywords: level shifter, differential amplifier, ground level 
Category: VLSI characterization 

Introduction: 
Challenges of characterizing digital cells start to look easy in the face of mixed signal cells with parameters that defy assumptions of digital cells. One of the assumption digital cells make is ground voltage is zero, which does not hold good for mixed signal cells like level shifter, differential amplifiers etc. How does delay measurement change with violation of this assumption is the topic of this article.

Below is an example waveform of such a cell.

multi threshold input and output waveforms of differential amplifier
Figure: multi rail wave forms of a differential amplifier 

Note that this cell appears to have differential input-pair and differential output pair. Input pair switch in different direction from zero volt to 0.73 volt, whereas output pair switched from 0.30 volt
to 0.68 volt.
Measuring Arc Delay: 
With changed voltages, one has to come up with new threshold voltages to find delay points. As we discussed in previous blog, delay measurement involves following 8 threshold voltages.
  • slew_low_rise_thr
    • A point close to low supply voltage in a rising voltage waveform used in measuring slope.
  • slew_high_rise_thr
    • A point close to high supply voltage in a rising voltage waveform used in measuring slope.
  • slew_low_fall_thr
    • A point close to low supply voltage in a falling voltage waveform used in measuring slope.
  • slew_high_fall_thr
    • A point close to high supply voltage in a falling voltage waveform used in measuring slope.
  • in_rise_thr
    • A voltage point in a rising voltage waveform at input port used in measuring delay.
  • in_fall_thr
    • A voltage point in a falling voltage waveform at input port used in measuring delay.
  • out_rise_thr
    • A voltage point in a rising voltage waveform at output port used in measuring delay.
  • out_fall_thr
    • A voltage point in a falling voltage waveform at output port used in measuring delay.
With these definition, we find rail swing for both input and output pins as follows:
  • in_rail_swing = pin_high_volt(in) - pin_low_volt(in)
  • out_rail_swing = pin_high_volt(out) - pin_low_volt(out)
Once swing has been determined, one can find input and output voltage levels crossing thresholds as follows:
  • in_volt = pin_low_volt(in) + in_thr*in_rail_swing
  • out_volt = pin_low_volt(out) + out_thr*out_rail_swing
One must substitute in_thr and out_thr definition from threshold table above, depending on the input and output transition. After that, delay of the cell is as simple as following subtraction:
delay = Timeout_volt - Timein_volt
Conclusion: 
In this article, we presented method and equations to compute delays with ground voltages other than zero. One can easily extend this method to find equation to compute output slope with ground voltages other than zero.
© Paripath Inc, 2015. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.

Negative delays aren't so negative after all !

posted Jan 20, 2015, 11:48 PM by Rohit Sharma   [ updated Jan 25, 2015, 9:05 AM ]

Keywords: Negative propagation delay, Standard cell delay, delay thresholds.
Category: VLSI characterization

Introduction
You read the term "negative delay" and your engineer mind goes racing creating science fictions - time machine, time generator, non-causal machine and so on. Here are the answers - no, you can't turn circuits with negative delays into a time-machine, you can't go back in time, you can't even increase frequency of a chip. So calm your nerves and allow us to debunk myths behind negative delays. In this article- we'll define delays, explain negative delays and sources thereof.

What is propagation delay?
Signal propagation delay is, nothing, but measurement of time between two signal. These two signals could be anywhere in the circuit, i.e. input and output pins of a cell, two nodes of an RC tree or start and end point of a time path.
In the context of a cell or circuit, change in input pins state could cause a change in output pin. Signal is said to have reached a point of no return in the transition, once it crosses a certain threshold. These thresholds are predetermined for the circuit. They could be different for rise and fall transition, input and output pin of a circuit or standard cell. These are typically set at 50 percent of the rail voltage (difference between power and ground voltages) of a signal. In this context rise or fall (propagation) delay of a circuit/cell is defined as

propagation delay = 50% threshold of output transition 
                    - 50% threshold of input transition
Under normal circumstances, propagation delay of a circuit/cell is positive, i.e. input signal reaches its 50% threshold before output signal reaches its 50% threshold.

But, how can delay go negative?
Sometimes cell (typically with strong drive strength) may exhibit negative propagation delay. This does not mean that standard cell's input and output have non-causal relationship. This is simply a manifestation of choice of delay threshold points. Picture below shows an example of negative delay of a simple inverter, when falling input A transition causes a rising transition at output Y.
Negative delay of standard cell (inverter circuit)

Figure: Negative Propagation Delay

It is easy to see in the picture that input signal A starts to fall at 0ps, whereas output signal does not move from low voltage (ground, VSS or 0.0V) until 235ps. This reinforces our earlier statement about causality of these two transition. Given rail voltage of 1.2 volt, delay threshold point of 50% translates in to a 0.6V of theshold. Notice that input reaches 0.6 Volt (50 percent threshold of input rail voltage) at 500ps, whereas output is able to reach this threshold 0.6 Volt (50 percent threshold of output rail voltage) at 467ps.
Using propation delay equation defined above,

propagation delay = 467ps - 500ps
                  = -33ps
And there, we witness negative delay for this transition.

So, what causes negative delays?
There could be many reasons for negative propagation delay of a circuit/cell, some of them are given below.
  • Poorly designed circuits,
  • Poor choice of delay thresholds,
  • Cell/circuit operating beyond their designed specifications,
  • Cell/circuit's asymmetric PMOS/NMOS drive strength operating under slow input transition time and used to drive small load.

Conclusion
In this article, we defined propagation delay. We, also, saw how a propagation delay could be negative and why does it not represent non-causal relationship between input and output. In the end, we outlined few probable causes of negative delays.

Credit
This blog was posted in response to following user question:
Q: What is negative propagation delay? by Lingraj Hiremath, Senior Design Engineer. Tata Elxi Limited.

© Paripath Inc, 2015. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.

Demystifying Slew Derate

posted Nov 22, 2014, 4:58 PM by Rohit Sharma   [ updated Nov 22, 2014, 5:54 PM ]

Keywords: slew derate from library, slew rate (aka transition time, slope), LibertyTM Format, STA (Static Timing Analysis)
Category: VLSI characterization

Introduction
Typically liberty library for process nodes below 40nm has a keyword called slew_derate_from_library. This keyword changes the way designers/EDA-tools read signal transition times (aka slew rate or slope) from library for both input and output pins of the cell. This keyword has bearing on other slew measurement thresholds, which makes whole picture a bit complex to comprehend. In this article, we'll try to explain slew dertate from characterization and timing analysis point of view.

Thresholds
Slew is measured between two thresholds - lower and upper. These threshold could be different for rising and falling transitions. Hence there are total of 4 different thresholds with following keywords
  • slew_lower_threshold_pct_fall : 30.0; 
  • slew_upper_threshold_pct_fall : 70.0;
  • slew_lower_threshold_pct_rise : 30.0;
  • slew_upper_threshold_pct_rise : 70.0;
These four thresholds are shown in the picture below

Liberty Slew Thresholds Definition
 
Need for slew derate
Signal slew rates for process nodes 180nm or above were linear between 10 and 90 percent of their rail voltages. This linearity drove the choice of slew thresholds between 10 percent and 90 percent. This linearity was reduced to a band of 20 percent and 80 percent for nodes between 180nm and 65nm. It was further reduced to 30 percent and 70 percent.

Latest transition band 30-70 percent is only 40 (70-30) percent of rail voltage, hence misrepresents slew rate between rail voltage. Need to translate this new band to a reasonable (more than 50 percent) percentage of rail voltage gave birth to slew derate.

Example
If we need to represent transition band of 30-70 percent to 10-90 percent, we'll be multiplying slew rates (aka transition times) measured between 30-70 percent by a factor of 2 to represent it as 10-90 percent. Slew rate is derived from these two bands. This is shown as a simple division below

    slew_derate_from_library = (70-30)/(10-90) = 0.5;

Slew derate for characterization
Input and output slew rates in liberty are stored after applying (i.e. dividing) slew_derate_from_library factor. Characterization software like guna applies signals with specified slew rate at inputs and measures slew at output. While reading slew rates from liberty, factor slew_derate_from_library is applied in a reverse fashion (by multiplying) in order to obtain slew rates between thresholds as specified in the liberty header (see Thresholds section above).

Input slew rates are multiplied by slew_derate_from_library factor to obtain slew rates between thresholds in the liberty header. Resulting input slew rate is extended to rail voltage, thereafter. Final input slew rate is applied in the form on piecewise linear voltage source at input. Assuming, rest of the inputs are tied to their appropriate signal voltage to cause output transition, characterization software measures output slew rate between thresholds as specified in the liberty header. This output slew rate is divided before being stored in new liberty file.

Slew derate for Timing Analysis
Timing analysis also reads slew rates from liberty file. Computing slew rate is further complicated by the fact that analysis software may read multiple liberty files with different thresholds and slew_derate_from_library factor. On the top of that, it may have it's own native slew thresholds (example - 20% to 80%). (Note that other types of derating like data/clock path derating is not covered in this article).

Timing analysis divides designs into timing stages. One Timing stage consists of driver model, net model and a receiver model. Driver model is derived from delay-slew/current/voltage values. Factor slew_derate_from_library is used is determining library slew between library threshold. Library thresholds are translated into timing analysis's native threshold using following equation

    slew valuelibrary-threshold = slew_derate_from_library * slew valuelibrary ;

Once, we have slew value between library threshold, it is easy to translate them into timing analysis' native threshold as follows:

    slewnative threshold = (native threshold / library threshold) * slewlibrary threshold

Summary
Slew derating is best understood by keeping in mind the following formula -
    slew valuelibrary-threshold = slew_derate_from_library * slew valuelibrary ;
© Paripath Inc, 2014. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.

Can Your Methodology Survive FinFET Variability?

posted Oct 15, 2014, 11:45 AM by Rohit Sharma   [ updated Oct 15, 2014, 1:03 PM ]

Keywords: FinFET structure, 14nm, 16nm, FinFET characterization, CCS Variation, LibertyTM Format, STA (Static Timing Analysis)
Category: VLSI characterization and variation

What is FinFET?
FinFET device is a three dimensional multi gate MOSFET transistor. Three dimensional FinFET structure contains channel grown over silicon substrate in third dimension with a gate wrapped around it as shown in the figure. 

FINfet transistor structure
Figure: FinFET transistor structure

It replaces planar MOSFET transistors with the ones with superior power and performance characteristics. FinFET devices are touted as disruptive technology to maintain the Moore’s Law trend of transistors count of a ICs doubling (approximately) every two years.

Good, Bad and Ugly Side of FinFETs

Good: Superior Power and Performance.
FinFET has superior IDsat properties compared to planar devices. This means faster transistors for same power or lower power for same speed compared to planar devices.

Bad: Higher Miller Capacitance
The 3D nature of the fins contributes to higher gate capacitance compared to planar devices. This increased gate capacitance directly impacts miller capacitance and its effect on stage delay and receiver waveform computation. In sub-20 nm, effect of miller capacitance on delay has jumped to more than 10 percent on a nominal delay of few hundred picoseconds and therefore can no longer be avoided.

Ugly: Higher Variation
There is a need to contain waveform distortion while sampling output and power-ground current and voltage waveforms. FinFET structure suffers more PVT (Process, Voltage, Temperature) variation than a planer process due to line- and fin-edge roughness.

4 Steps to Avoid Characterization Pitfalls with FinFETs
  1. Characterize for more voltage, temperatures and process convers to avoid k-factor interpolation accuracy loss. 
  2. Few cells have more voltage variation than other. Voltage variation binning of cells and targeting limiting low variation cells to low voltage islands will limit variation range. 
  3. Employ sophisticated OCV (On Chip Variation) strategy with advanced models characterized with modern software like guna.
  4. Make sure to use a software that understands accuracy impact of characterization on static analyses. One such available technology is context aware models.

© Paripath Inc, 2014. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.


Comparing NLDM And CCS delay models

posted Sep 19, 2014, 3:01 PM by Rohit Sharma   [ updated Nov 24, 2015, 8:25 PM ]

VLSI characterization timing model
Keywords: CCS (Composite Current Source), NLDM (Non Linear Delay Model), SDM (Simplified Driver Model), STA (Static Timing Analysis)

What is timing model?
A timing model consists of driver model, net model and a receiver model. Driver model and receiver models are typically characterized using a circuit simulator, whereas net model is either estimated (wire-load, manhattan or star topology) or extracted from a layout using technology parameters of metal, via and contact etc.
Static Timing Delay Calculation Model
Figure: Timing Delay Calc Model

NLDM Driver Model
NLDM driver model characterizes input-to-output delay and output transition times with sensitivity to input transition time, output load and side input states. These characteristics are obtained using a circuit simulator with appropriate stimulus to cause output transition. Input stimulus along with input/output measurement/capture points are shown in the picture below.
NLDM driver model characterization
Figure: NLDM driver model characterization

As seen in the picture, characterization software like guna measure and captures 3 points on sides of active input and active output. These three points are called delay and transition time thresholds. Difference between input delay threshold and output delay threshold is modeled as cell delay and difference between lower and upper transition times on output port is modeled as output transition time. These two parameters - delay and transition times are used to synthesize NLDM driver model shown in the picture below:
NLDM Driver Model
Figure: NLDM driver model 

NLDM Receiver Model
NLDM receiver model is simply a single capacitor for the entire transition with no sensitivity.

Shortcomings of NLDM model
NLDM only captures 3 output points, which is not sufficient to reflect non-linearities of circuits at lower geometries (65nm and below) in synthesized driver model during static timing analysis. Classical case of this insufficiency is when driver resistance is order of magnitude less than the impedance of net it is driving (Rd << Znet). Driver model requires more granularity in driver model. CCS timing model eliminate need for this synthesis and hence is able to achieve higher accuracy than NLDM.

Other significant shortcoming of NLDM is in the receiver model. NLDM receiver model fails capture miller effect. This effects dominates delay calculation of STA for very small impedance nets.

CCS Driver Model
CCS driver model is characterized by capturing current waveform flowing into the load capacitor of the cell. CCS driver model also has sensitivity to input transition time, output load and side input states. CCS driver model is essentially a current source with infinite driver resistance, hence it provides better accuracy in cases where net impedance is very very high. Note, CCS timing model does not require synthesis of driver model, captured current waveform is driver model itself.
CCS Driver Model
Figure: CCS (Composite Current Source) Driver Model

CCS Receiver Model
CCS receiver model is characterized much like NLDM receiver model with additional granularity to reflect sensitivities like miller capacitance, state of side inputs, input transition times and output load. To accurately reflect effect of miller capacitance on input capacitance and net-delay, it is divided into two parts - C1 and C2. For STA delay calculation, C1 is used in net delay calculation before receiver waveform hits delay threshold point and C2 is used in net delay calculation after receiver waveform hits delay threshold point.
CCS receiver Model
Figure: Composite Current Source Receiver Model

Summary
In this article, we introduced timing model of a VLSI cell. We discussed NLDM (Non Linear Delay Model) of a cell used in STA. In later section, we highlighted shortcomings of NLDM for advanced nodes and CCS (Composite Current Source) as one solution to address them.



© Paripath Inc, 2014. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.



Standard Cell Characterization

posted Aug 31, 2014, 7:15 AM by Rohit Sharma   [ updated Sep 6, 2014, 8:46 AM ]

What is cell characterization?
Cell characterization is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.

Why is cell characterization needed?
No digital chip is possible without cell models. These cell models are produced by cell characterization using commercial softwares like guna. Every digital chip implementation (rtl-to-gdsII) flow requires cell models for analysis (logic simulation, verification, timing, power, noise etc), implementation (synthesis, test insertion, placement, clock tree synthesis, routing) and fixing (engineering change order, rule fixing etc).

How is cell characterization performed?
Cell characterization typically takes cell design extracted as spice circuit and spice technology models. Characterization software like guna from Paripath, analyzes this information to 
  1. acquire or recognize cell's function, 
  2. generates stimulus appropriate to determine characteristic (like delay, transition time etc), 
  3. simulates it using circuit simulator, 
  4. gather simulations output to measure characteristic and 
  5. finally writes this data into a standard like libertyTM, veriog or IBIS. 
This entire flow is depicted into the picture shown below

Standard Cell Characterization Flow

Figure: cell characterization flow

Cell characterization output
Cell characterization produces following outputs, in no particular order
  1. verilog
  2. IBIS
  3. libertyTM Format
    1. Delay
    2. Transition Time
    3. Tristate
    4. Input Capacitance
    5. Hidden Power
    6. Glitch Power
    7. Dynamic Power
    8. Leakage Power
    9. Setup Time
    10. Hold Time
    11. Recovery Time
    12. Removal Time
    13. Minimum Pulse Width
    14. Output Current Waveform
    15. Input Receiver Capacitance
    16. Power Supply Waveforms
    17. Ground Waveforms
    18. Leakage Current
    19. Gate Leakage Current
    20. CCB Output VIVO 
    21. CCB Output Voltage Waveform
    22. CCB Input Miller Capacitance
    23. CCB Noise Propagation Model
    24. ... and other
Summary
This article answers main questions on standard cell characterization and model generation. Scope of this topic is VLSI cell/circuits. Please google for solar cell characterization and bio-cell characterization. Read more on VLSI characterization on Paripath Blog.
© Paripath Inc, 2014. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.

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Miller Capacitance Characterization

posted Aug 25, 2014, 6:21 PM by Rohit Sharma   [ updated Sep 2, 2014, 12:49 PM ]

Keywords: cell characterization, input capacitance characterization

What is miller capacitance?
Simply put- miller capacitance is nothing but coupling capacitance between input and output of a circuit. This effect was first identified by John Milton Miller - a noted electrical engineer of twentieth century.
Increase in input capacitance of an electrical circuit, caused by presence of miller capacitance is called Miller effect. This phenomenon is more generally described in Miller Theorem.

Why is Miller capacitance important?
Miller capacitance changes node/pin capacitance of a circuit. This changed capacitance, if not captured accurately during circuit characterization impacts accuracy of all analyses including static timing analysis, power analysis and noise analysis among others.

Characterization of miller capacitance
This is a general proof, and is applicable to circuits of all logic families including TTL, ECL and CMOS and others. Later we'll limit our attention to cmos circuits and attempt to simplify characterization method.
Generic buffer/amplifier setup for miller capacitance characterization
In the picture, miller capacitance is shown as CM connected across a buffer/amplifier. Also connected is input capacitance Ci at input and voltage source Vo at output. Assuming current flowing in the buffer is negligible, Kirchoff Current Law dictates that current flowing in two capacitors is equal:
Miller Capacitance Equation 1
If we change value of input capacitance as C1 and C2 at input, apply two voltage sources Vo1 and Vo2 at the output, we can measure changed voltage across Ci1 and Ci2 as Vi1 and Vi2 respectively. Putting these values in equation above, we get
Miller Capacitance Equation 2
This equation is useful for determining driver strengthening (weakening) by aggressor during noise analysis. To find increase in input capacitance, one can exchange Ci and Vi nodes and apply same equation to find miller capacitance. Input miller capacitance is a useful metric for static timing and power analysis. Characterizing input miller capacitance in isolation, however, is not very useful in static analyses. Since static methods will be needed to compute increased loading effect of miller capacitance.

One such method will be to use miller coefficient. This is only a coarse approximation. More accurate, computationally efficient and industry prevalent method is to account for miller capacitance during input/receiver capacitance characterization. Modern current source models (CCS and ECSM) granularize input/receiver capacitance to capture dynamic effect of miller capacitance.

Deriving miller capacitance
If we limit our attention to CMOS inverter, we can derive miller capacitance simply by adding gate-to-drain and gate-to-source capacitance of PMOS and NMOS transistors respectively. These capacitance are shown in the picture below.
CMOS intverter miller capacitance
This simplification, however, is not accurate in practice because it ignores other parasitic resistors and capacitors contributed by poly, diffusion, metal, via and other circuit components.

Summary
We discussed definition and importance of miller capacitance. We also presented two different method to determine miller capacitance. We compared their accuracy and applicability to different logic families.

© Paripath Inc, 2014. Unauthorized use and/or duplication of this material without express and written permission from this blog’s owner is strictly prohibited. Excerpts and links may be used, provided that full and clear credit is given to Paripath Inc with url www.paripath.com and specific direction to the original content.

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Translating CCS timing model into ECSM timing model and vice-versa

posted Aug 12, 2014, 2:56 PM by Rohit Sharma   [ updated Sep 2, 2014, 12:53 PM ]


keywords: CCS (Composite Current Source), ECSM (Effective Current Source Model), STA (Static Timing Analysis)

Delay calculator of static timing analysis engine looks up CCS or ECSM timing models in liberty file, interpolate or extrapolates neighboring points before it uses them in static timing analysis. CCS driver model captures output current flowing through load capacitor. Thus CCS model forces characterization engine to have a non-zero capacitance connected to cell's output. ECSM driver model captures voltage waveform at cell's output. ECSM driver model can capture load sensitivity starting from zero load capacitance, whereas CCS must start from non-zero load capacitor.
cmos inverter voltage current profile
Inverter's current/voltage profile

In the next section, we'll relate these two driver model using basic circuit theory, which defines charge as:
charge across capacitor (q=cv)
where 
q=charge stored in capacitor, 
C=capacitance 
v=voltage across capacitor

Also, Current is a measurement of the flow of electricity and is generally describe as
charge-current equation

Combining these two equations, gives us
current over time through capacitor equation

differentiating and integrating both sides w.r.t time, yields 
current through and voltage across capacitor

These two equations enlighten us that current and voltage is nothing but two faces of charge stored in capacitor. And current can be computed from voltage and vice-versa.

Remember, we said earlier that CCS driver model captures output current flowing through load capacitor and ECSM driver model captures voltage waveform at cell's output. Since we've shown that current can be computed from voltage and vice-versa, it is easy to see that CCS driver model can be derived from ECSM driver and vice-versa.

There are practical accuracy limitations, however. ECSM voltage and CCS current waveform are sampled with far fewer points - typically 10 to 100 times fewer points from reference simulator's output. There is limited accuracy loss, when these points are sampled judiciously from circuit simulator's output. Accuracy loss may become pronounced, in case sampled ECSM voltage waveform is translated into CCS current waveform (and vice-versa) because of missing data.
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CCS Timing Model vs ECSM Timing Model

posted Aug 12, 2014, 11:25 AM by Rohit Sharma   [ updated Nov 24, 2015, 8:29 PM ]

CCS stands for Composite Current Source and ECSM stands for Effective Current Source Model. Both of these are current source models and have ability to abstract circuit models for static timing, power, noise and voltage-drop analysis.

Timing model consists of a driver model and a receiver model as shown in next picture.
Delay Calculation Model with Driver and Receiver

Delay calculator of static timing analysis engine looks up, interpolate or extrapolates these two models in liberty. CCS driver model captures output current flowing through load capacitor. Thus CCS model forces characterization engine to have a non-zero capacitance connected to cell's output. ECSM driver model captures voltage waveform at cell's output. ECSM driver model can capture load sensitivity starting from zero load capacitance, whereas CCS must start from non-zero load capacitor. Next picture shows output voltage V(CY) captured in ECSM driver model and output current I(CY) captured in CCS driver model.

CMOS Inverter Voltage and Currents

Next picture shows miller capacitance of inverter contributed by both transistors - nmos and pmos. Receiver model of both models captures miller capacitance of receiver with sensitivity to slope and load. 

Miller capacitance (C_gs.nmos + C_gd.pmos)

In the next blog, we'll relate these two driver model using basic circuit theory. Current source receiver models are essentially same with different granularity. Both these CCS and ECSM models capture miller effect as input capacitance with different sensitivity to input transition, input transition times, output load etc.

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