Can Your Methodology Survive FinFET Variability?

Post date: Oct 15, 2014 6:45:24 PM

It replaces planar MOSFET transistors with the ones with superior power and performance characteristics. FinFET devices are touted as disruptive technology to maintain the Moore’s Law trend of transistors count of a ICs doubling (approximately) every two years.

Good, Bad and Ugly Side of FinFETs

Good: Superior Power and Performance.

FinFET has superior I_Dsat properties compared to planar devices. This means faster transistors for same power or lower power for same speed compared to planar devices.

Bad: Higher Miller Capacitance

The 3D nature of the fins contributes to higher gate capacitance compared to planar devices. This increased gate capacitance directly impacts miller capacitance and its effect on stage delay and receiver waveform computation. In sub-20 nm, effect of miller capacitance on delay has jumped to more than 10 percent on a nominal delay of few hundred picoseconds and therefore can no longer be avoided.

Ugly: Higher Variation

There is a need to contain waveform distortion while sampling output and power-ground current and voltage waveforms. FinFET structure suffers more PVT (Process, Voltage, Temperature) variation than a planer process due to line- and fin-edge roughness.

4 Steps to Avoid Characterization Pitfalls with FinFETs

1. Characterize for more voltage, temperatures and process convers to avoid k-factor interpolation accuracy loss.
2. Few cells have more voltage variation than other. Voltage variation binning of cells and targeting limiting low variation cells to low voltage islands will limit variation range.
3. Employ sophisticated OCV (On Chip Variation) strategy with advanced models characterized with modern software like guna.
4. Make sure to use a software that understands accuracy impact of characterization on static analyses. One such available technology is context aware models.